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h anb it HDD32M64F8K url : www.hbe.co.kr 1 hanbit electronics co.,ltd. rev 1.0 (august.2002) general description th e HDD32M64F8K is a 32 m x 64 bit double data rate(ddr) synchronous dynamic ram high - density memory module. the module consists of sixteen cmos 16 m x 8 bit with 4banks ddr sdram s in 66pin tsop - ii 400mil package s and 2k eeprom in 8 - pin tssop package on a 200 - pin glass - epoxy. four 0. 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the hsd32m64f8k is a s mm (stackable memory module type) . synchronous design allows precise cycle control wi th the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory syste m applications . a ll module components may be powered from a single 2.5 v dc power supply and all inputs and outputs are sstl_2 compatible. features ? p art identification HDD32M64F8K C 10a : 1 00 mhz (cl= 2 ) HDD32M64F8K C 13a : 1 33 mh z (cl= 2 ) HDD32M64F8K C 13b : 1 33 mhz (cl= 2.5 ) ? 256mb(32mx64) unbuffered ddr smm based on 16 mx8 ddr sdrsm ? 2.5v 0.2v vdd and vddq power supply ? auto & self refresh capability ( 4096 cycles/64ms) ? all input and output are compatible with sstl_2 interf ace ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? mrs cycle with address key programs - latency (access from column address) : 2, 2.5 - burst length : 2, 4, 8 - data scramble : sequential & interleave ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except dat a(dq), data strobes and data masks latched on the rising edge s of the clock ? the used device is 4m x 8bit x 4banks ddr sdram ddr sdram module 256mbyte (32mx64bit), based on16mx8,4banks, 4k ref., smm, part no . h dd32m64f8k
h anb it HDD32M64F8K url : www.hbe.co.kr 2 hanbit electronics co.,ltd. rev 1.0 (august.2002) pin assignment p1 p2 pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 /cs0 35 dq15 69 nc 1 vddq 35 dq 17 69 nc(dqs8) 2 /cs1 36 dq14 70 dqs1 2 a3 36 dq18 70 dqs3 3 vss 37 vddq 71 dqs5 3 vss 37 vddq 71 dqs6 4 cke0 38 dq13 72 vdd 4 a2 38 dq19 72 vdd 5 cke1 39 dq12 73 nc 5 a1 39 dq20 73 dq56 6 nc 40 dq11 74 dq39 6 a0 40 dq21 74 dq57 7 vdd 41 vss 75 dq38 7 vdd 41 vss 75 dq58 8 ck0 42 dq10 76 vss 8 a10 42 dq22 76 vss 9 ck1 43 dq9 77 dq37 9 a11 43 dq23 77 dq59 10 nc 44 dq8 78 dq36 10 ba0 44 nc(cb6) 78 dq60 11 vss 45 vdd 79 vddq 11 vss 45 vdd 79 vddq 12 nc 46 *sa0 80 dq35 12 ba1 46 nc(cb4) 80 dq61 13 dm 0 47 *sa1 81 dq34 13 dm2 47 nc(cb2) 81 dq62 14 dm4 48 vss 82 dq33 14 dm6 48 vss 82 dq63 15 vddq 49 *sa2 83 vss 15 vddq 49 nc(cb0) 83 vss 16 nc 50 vddq 84 dq32 16 nc 50 vddq 84 dq55 17 nc 51 vdd 85 dq40 17 nc 51 vdd 85 dq54 18 vss 52 /ras 86 dq41 18 vs s 52 a4 86 dq53 19 nc 53 vss 87 vddq 19 dqs7 53 vss 87 vddq 20 dqs0 54 /cas 88 dq42 20 dqs2 54 a5 88 dq52 21 dqs4 55 /ck0 89 dq43 21 nc 55 a6 89 dq51 22 vdd 56 /ck1 90 dq44 22 vdd 56 a7 90 dq50 23 nc 57 vdd 91 vss 23 dq31 57 vdd 91 vss 24 dq0 58 /ck2 92 dq45 24 dq30 58 a8 92 dq49 25 dq1 59 ck2 93 dq46 25 dq29 59 a9 93 dq48 26 vss 60 /we 94 dq47 26 vss 60 nc(a12) 94 nc(cb7) 27 dq2 61 vss 95 *scl 27 dq28 61 vss 95 vdd 28 dq3 62 nc 96 *wp 28 dq27 62 dm3 96 nc(cb5) 29 vddq 63 dm1 97 *vspd 29 vddq 63 dm7 97 nc(cb3) 30 dq4 64 dm5 98 vss 30 dq26 64 nc(dm8) 98 vss 31 dq5 65 vddq 99 *sda 31 dq25 65 vddq 99 nc(cb1) 32 dq6 66 nc 100 vddin 32 dq24 66 nc 100 vdd 33 vss 67 vref 33 vss 67 nc(a13) 34 dq7 68 vss 34 dq16 68 vss * these pins should be nc in the system which does not support spd pin pin description pin pin description a0~a11 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for dqs(2.5v) dq0~dq63 data input/output vref power supply for reference cb0~ cb7 check bit(data input/output) vspd serial eeprom power supply(3.3) dqs0~dqs7 data strobe input/output vss ground dm0~dm7 data - in mask sa0~sa2 address in eeprom ck0~ck2,/ck0~/ck2 clock input sda serial data i/o cke0~cke1 clock enable input scl serial clock /cs0~/cs1 chip select input wp write protection /ras row address strobe vddin vdd indentification flag /cas column address strobe nc no connection
h anb it HDD32M64F8K url : www.hbe.co.kr 3 hanbit electronics co.,ltd. rev 1.0 (august.2002) u1 u2 u3 u4 u5 u6 u8 u9 u10 u11 u13 u14 u15 u16 u18 u19 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/ o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/ o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 stacking ? ?? ?? ?? f unctional block diag ram
h anb it HDD32M64F8K url : www.hbe.co.kr 4 hanbit electronics co.,ltd. rev 1.0 (august.2002) pin function description pin name input function ck, / ck clock ck and ck are differential clock inputs. all address and control input signals are sam - pled on the positive edge of ck and negative edge of ck. output (read) data is referenced to both edges of ck. interna l clock signals are derived from ck/ck. cke clock enable cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power - down and self refresh operation (all banks idle), or active power - down(row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power - down and self refresh modes, p roviding low standby power. cke will recognize an lvcmos low level prior to vref being stable on power - up. /cs chip select cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. a0 ~ a1 1 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra1 1 , column address : ca0 ~ ca 9 ba0 ~ ba1 bank se lect address b a0 and ba1 define to which bank an active, read, write or pre - charge command is being applied. / ras row address strobe latches row addresses on the positive going edge of the clk with / ras low. enables row access & precharge. / cas columnadd ress strobe latches column addresses on the positive going edge of the clk with / cas low. enables column access. / we write enable enables write operation and row precharge. latches data in starting from / cas, / we active. dq s 0 ~ 7 data strobe output with read data, input with write data. edge - aligned with read data, cen - tered in write data. used to capture write data. dm0~7 input data mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load - ing. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. wp write protection wp pin is connec ted to vcc. when wp is high , eeprom programming will be inhibited and the entire memory will be write - protected. vddq supply dq power supply : +2.5v 0.2v. vdd supply power supply : +2.5v 0.2v (device specific). vss supply dq ground. vref supply s stl_2 reference voltage.
h anb it HDD32M64F8K url : www.hbe.co.kr 5 hanbit electronics co.,ltd. rev 1.0 (august.2002) absolute maximum rat ings parameter symbol rating unte voltage on any pin relative to vss v in , v out - o.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipation p d 16.0 w short circuit current i os 50 ma notes: operation at above absolute maximum rating can adversely affect device reliability dc operating con ditions ( recommended operating conditions (vo ltage referenced to v ss = 0v, t a = 0 to 70 c) ) parameter symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 1.15 1.35 v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v input low voltage v il (dc) - 0.3 v ref - 0.15 v input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v input differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v input le akage current i l i - 2 2 ua 3 out put leakage current i oz - 5 5 ua out put high current (v out = 1.95v) i oh - 16.8 ma out put low current (v out = 0.35v) i o l 16.8 ma notes : 1.typically, the value of v ref is expected to be about 0.5* v dd of the transmi tting device . v ref is expected to track variation in v ddq . 2.peak to peak ac noise on v ref may not exceed 2% v ref (dc). 3.v tt of the transmitting device must track v ref of the receiving device. capacitance ( v dd = min to max, v ddq = 2.5v to 2.7v, t a = 2 5 c, f = 1 00 mhz ) description symbo l min max units input capacitance(a0~a11, ba0~ba1, / ras, / cas ,/we) c in1 93 107 pf input capacitance(cke0,cke1) c in2 63 77 pf input capacitance(/cs0~/cs1) c in3 58 72 pf input capacitance(clk0, clk1,clk2) c in4 30 45 pf i nput capacitance(dm0~dm7) c in5 10 15 pf d ata input/output capacitance (dq0 ~ dq 63, dqs0~dqs7 ) c out1 10 15 pf
h anb it HDD32M64F8K url : www.hbe.co.kr 6 hanbit electronics co.,ltd. rev 1.0 (august.2002) d c characteristics (recommended operating condition unless otherwise noted, v dd = 2.5v, t = 25 c) version note parameter symbo l test condition - 10a - 13a - 13b unit operating current (one bank active) i dd1 burst length = 2 t rc 3 t rc (min) , cl=2.5 i o ut = 0ma , active - read - presharge 1520 1600 1600 ma precharge standby current in power - down mode i dd2p cke v il (max) t c k = t ck (min) , all banks idle 48 56 56 ma precharge standby current in non power - down mode i dd2n cke 3 v ih (min) / c s 3 v ih (min), t c k = t ck (min) 288 320 320 ma active standby current in power - down mode i dd 3 p all banks idle, cke v il (max), t c k = t ck (min) 480 560 560 ma active standby current in non power - down mode (one bank active) i dd 3 n onel banks, active - read - presharge, t rc = t ras (max) , t c k = t ck (min) 720 800 800 ma cl=2. 5 operating current ( read ) i dd 4r burst length = 2 t rc = t rc (min) , i o ut = 0ma , cl=2 1840 2160 2160 ma cl=2. 5 operating current ( write) i dd 4w burst length = 2 t rc = t rc (min) cl=2 1840 2240 2240 ma auto refre sh current i dd 5 t rc 3 t ref (min) 2720 2880 2880 ma self refresh current i dd 6 cke 0.2v 32 32 32 ma ac operating condition s parameter s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) vref + 0.35 input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) vref - 0.35 v input differential voltage, ck and ck inputs v id (ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*vddq - 0.2 0.5*vddq+0.2 v 2 notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of v ix is expected to equal 0.5* v ddq of th e transmitting device and must track variations in the dc level of the s ame
h anb it HDD32M64F8K url : www.hbe.co.kr 7 hanbit electronics co.,ltd. rev 1.0 (august.2002) ac operating test conditions parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 1.0 v input levels( v i h / v i l ) v re f +0.35/ v re f v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit v a c c haracteristics (these ac charicteristics wer e tested on the component) ddr200 ddr266a ddr266b - 10a - 13a - 13b parameter symbo l min max min max min max unit note row cycle time t rc 70 65 65 ns 1 refresh row cycle time t rfc 80 75 75 ns 1,2 row active time t ras 48 120k 45 120k 45 120k ns 1,2 / ras to / cas delay t rcd 20 20 20 ns 3 row precharge time t rp 20 20 20 ns 3 row active to row active delay t rrd 15 15 15 ns 3 write recovery time t wr 2 2 2 t ck 3 last data in to read command t cdlr 1 1 1 t ck 2 col. address to col . address delay t ccd 1 1 1 t ck cl=2.0 10 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 12 7.5 12 7.5 12 ns
h anb it HDD32M64F8K url : www.hbe.co.kr 8 hanbit electronics co.,ltd. rev 1.0 (august.2002) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out acc ess time from ck/ck t dqsck - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - +0.6 - +0.5 - +0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck data out high impedence time from ck - /ck t hzq - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns 2 ck to valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0.25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold time t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqsh 0.35 0.35 0.35 t ck dqs - in low level width t dqs l 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time t is 1.1 0.9 0.9 ns address and control input hold time t ih 1.1 0.9 0.9 ns mode register set cycle time t mrd 16 15 15 ns dq & dm setup time to dqs t ds 0.6 0.5 0.5 ns dq & dm hold time to dqs t dh 0.6 0.5 0.5 ns dq & dm input pulse width t dipw 2 1.75 1.75 ns power down exit time t pdex 10 10 10 ns exit self refresh to write command t xsw 116 95 ns exit self refresh to bank active command t xs a 80 75 75 ns exit self refresh to read command t xs r 200 200 200 cycle refresh interval time t ref 15.6 15.6 15.6 us 1 output dqs valid window t q h 0.35 0.35 0.35 t ck dqs write postamble time t w pst 0.25 0 .25 0.25 t ck 4 notes : 1. maximum burst refresh of 8. 2. t hzq transitions occurs in the same assess time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer drivi ng. 3. the specific requirement is that dqs be valid (high - low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss .
h anb it HDD32M64F8K url : www.hbe.co.kr 9 hanbit electronics co.,ltd. rev 1.0 (august.2002) 4. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. simplified truth tab le command cke n - 1 cke n /cs /r a s /c a s /we dm ba 0,1 a10/ ap a11 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refres h exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address (a0 ~ a 9 ) 4 auto precharge dis able h l 4 write & column address auto precharge en able h x l h l l x v h column address (a0 ~ a 9 ) 4,6 burst stop h x l h h l x x 7 bank selection v l precharg e all banks h x l l h l x x h x 5 h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a1 1 & ba0 ~ ba1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. au to refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. if both ba0 and b a1 are "low" at read, write, row active and precharge, bank a is selected. if both ba0 is "low" and ba1 is "high" at read, write, row active and precharge, bank b is selected. if both ba0 is "high" and ba1 is "low" at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are "high" at read, write, row active and precharge, bank d is selected. if a10/ap is "high" at row precharge, ba0 and ba1 is ignored and all banks are selected.
h anb it HDD32M64F8K url : www.hbe.co.kr 10 hanbit electronics co.,ltd. rev 1.0 (august.2002) 5. during burst read or write with auto precharge , new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dm s ampled at the rising and falling edges of the dqs and data - in are masked at the both edges ( write dm latency is 0 ) p ackaging information unit : mm front C side rear - side
h anb it HDD32M64F8K url : www.hbe.co.kr 11 hanbit electronics co.,ltd. rev 1.0 (august.2002) o r dering information part number density org. package ref. vcc mode max.frq HDD32M64F8K - 10a 256mbyte 32m x 64 200pin smm 4k 2.5v ddr 100mhz/cl2 HDD32M64F8K - 13a 256mbyte 32m x 64 200pin smm 4k 2.5v ddr 133mhz/cl2 HDD32M64F8K - 13b 256mbyte 32m x 64 200pin smm 4k 2.5v ddr 133mhz/cl2.5

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